The present invention relates generally to multi-chip memory packages and methods of fabricating same. More particularly, the invention is related to multi-chip memory packages in which fabrication process variations are compensated.
As the size of mobile electronic devices decreases, the packaged semiconductor memories incorporated within these devices must be fabricated with ever more compact and lightweight designs. Reductions in size, weight and current consumption notwithstanding, semiconductor memories must operate at high speed with increased bandwidth. As a result, legacy electronic mobile devices included single-chip package memories. More recently, electronic mobile devices include multi-chip package memories formed by stack connecting a plurality of memory chips, wherein the plurality of memory chips may provide different types of memory system functionality.
In a conventional multi-chip package memory, constituent memory chips are stacked on an interface chip (e.g., a memory controller) using one or more of a number of available stacking techniques.
For example, within a conventional multi-chip package memory, first, second, and third memory chips may be physically stacked one on top of the other and the respective memory chips electrically connected to signal pads with bonding wires. That is, the first memory chip is electrically connected to a first pad with a first bonding wire, the second memory chip is electrically connected to a second pad with a second bonding wire, and the third memory chip is electrically connected to a third pad with a third bonding wire.
Alternately, a plurality of memory chips may be stack connected using vertical connection elements, such as through silicon vias (TSVs). The term TSV reads on a range of connection elements associated with a through hole via (THV). For example, where first, second, and third memory chips are stack connected, a TSV may be formed between the first memory chip and the second memory chip such that one or more signals may be communicated by the TSV formed the first memory chip to the second memory chip. In similar vein, another TSV may be formed between the second memory chip and the third memory chip, etc. In this manner, a collection of vertical connection elements may form a connection path through a stacked plurality of memory chips.
Unfortunately, stack connection approaches relying on vertical connection paths formed by multiple vertical connection elements are inherently susceptible to process variations in the manufacture of individual memory chips and related packaging processes. In particular, various process variations may result in different signal flight times between input/output (I/O) points within the stacked plurality of memory chips and/or different computational processing times for like elements between different memory chips and related circuits. For example, the first memory chip in a stacked plurality of memory chips may return read data in response to a read command applied to the multi-chip package memory with very different timing than the third chip in the same stack.